Tech. Details On Memory (RAM)

[tareek]

Chapter 01 :

Tech Details of Different Types Of Memory :

-------------------------------------------------------------------------
|  RAM Feature Type       |  (SDR) SDRAM         |    DDR(1) SDRAM      |
|-------------------------|----------------------|----------------------|
| Clock frequency         | 100/133/166 MHz      | 100/133/166/200 MHz  | 
| Transfer data rate      | 100/133/166 MHz      | 200/266/333/400 MHz  | 
| I/O width               | ×16 / ×32            | ×4 / ×8 / ×16 / ×32  |
| Prefetch bit width      | 1bit                 | 2bits                |
| Clock input             | Single clock         | Differential clock   |
| Burst length            | 1, 2, 4, 8, full page| 2, 4, 8              |
| Data strobe             | Unsupported          | Bidirectional Data   |
|                         |                      | Strobe (single ended)|
| Supply voltage          | 3.3V/2.5V            | 2.5V                 |
| Interface               | LVTTL                | SSTL_2               |
| CAS latency (CL)        | 2, 3 clock           | 2, 2.5, 3 clock      |
| Read latency            | CL                   | CL                   |
| Write latency           | 0                    | 1                    |
| Additive latency (AL)   | Unsupported          | Unsupported          |
| Off-chip driver (OCD)   | Unsupported          | Unsupported          |
| On die termination (ODT)| Unsupported          | Unsupported          |
| Component package       | TSOP(II)/FBGA        | TSOP(II)/FBGA/LQFP   |
| pin (module)            | 168pin               | 184pin               |
|                         |                      |                      |
|-------------------------|----------------------|----------------------|

---------------------------------------------------------------------------
|   RAM Feature Type      |      DDR2 SDRAM          |    DDR3 SDRAM      |
|-------------------------|--------------------------|--------------------|
| Clock frequency         | 200/266/333/400 MHz      | 400 ~ 800 MHz      |
| Transfer data rate      | 400/533/667/800 MHz      | 800 ~ 1600 MHz     |
| I/O width               | ×4 / ×8 / ×16            | ×4 / ×8 / ×16      |
| Prefetch bit width      | 4bits                    | 8 bit              |
| Clock input             | Differential clock       | Differential clock |
| Burst length            | 4, 8                     |                    |
| Data strobe             | Bidirectional Data Strobe|                    |
|                         | (single ended or         |                    |
|                         | differential) with RDQS  |                    |
| Supply voltage          | 1.8V                     | 1.5v               |
| Interface               | SSTL_1.8                 |                    |
| CAS latency (CL)        | 3, 4, 5 clock            |                    |
| Read latency            | AL+CL                    |                    |
| Write latency           | (AL+CL)-1                |                    |
| Additive latency (AL)   | 0, 1, 2, 3, 4 clock      |                    |
| Off-chip driver (OCD)   | Support/Present          | Support            |
| On die termination (ODT)| Support/Present          | Support            |
| Component package       | FBGA                     | FBGA               |
| pin (module)            | 240 pin                  |                    |
|                         |                          |                    |
|-------------------------|--------------------------|--------------------|

-------------------------------------------------------------------------
| RAM Type                |    XDR DRAM        | DDR4 SDRAM | QDR SDRAM |
|-------------------------|--------------------|------------|-----------|
| Clock frequency         | 400 MHz ~          |            |           |
| Transfer Data Rate      | 3.2 GHz ~          |            |           |
| I/O Width               | x16                |            |           |
| Prefetch bit width      |                    |            |           |
| Clock Input             | Differential clock |            |           |
| Burst length            |                    |            |           |
| Data Strobe             |                    |            |           |
| Supply Voltage          | 1.8v               |            |           |
| Interface               |                    |            |           |
| CAS Latency(CL)         |                    |            |           |
| Read Latency            |                    |            |           |
| Write Latency           |                    |            |           |
| Additive Latecny        |                    |            |           |
| Off-Chip Driver         | Support            |            |           |
| On Die Termination      | Support            |            |           |
| Component Package       | FBGA               |            |           |
| pin (module)            |                    |            |           |
|                         |                    |            |           |
|-------------------------|--------------------|------------|-----------|

CAS : Column Address Select/Strobe . The lower the (CL) CAS value, the faster the RAM is .
Faster speed, faster RAM .
The more Data bit width, the more total Bandwidth is .

SDR : Single Data Rate SDRAM . 1 data word in 1 clock cycle (in rising edge) . Single port for read, write .

DDR : Double Data Rate SDRAM . 2 data words in 1 clock cycle (in both rising & falling edge) . Single port for read, write .

XDR : eXtreme Data Rate DRAM . Bi-Directional RSL (DRSL) (Differential Rambus Signaling Levels), FlexPhase, ODR .

QDR : Quad Data Rate SDRAM . 4 data words in 1 clock cycle. Separate read, write port .

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Chapter 02 :

GBps = GB/s . Giga Bytes Per Second (Bandwidth / Through-put Speed) . BW = Bandwidth . GT/s = Giga (/Billion) Transition (or, Transfer) per Second (Bandwidth) . MHz = Mega (Million) Hertz (Frequency) (Speed) . GHz = Giga (Billion) Hertz (Frequency) . RAM = Random Access Memory . SRAM = Static RAM . ROM = Read Only Memory . EDO = Extended Data Out RAM . FPM = Fast Page Mode DRAM . DRAM = Dynamic RAM . SDRAM = Synchronous DRAM . DDR = Double Data Rate . QDR = Quad Data Rate . ODR = Octal Data Rate . GDDR = Graphics DDR SDRAM . DCT = DRAM Controller . MCT = Memory Controller . 1 Ch = One/Single Channel . 2 Ch = Dual/2/Double Channel . 4 Ch = Quad/4 Channel . DP = Double Pumped . FSB = Front Side Bus . I/O = Input/Output . JEDEC = Joint Electronic Device Engineering Council . BIOS = Basic Input Output System .

In DRAM, memory data bits are maintained by a refresh circuit/logic, data survives because of this continuous refreshing action, that's why it is called dynamic, without it, data would get lost . DRAM is slower than SRAM . But DRAM is cheaper to construct, as it requires less electronic components than SRAM .

* SIMM : Single In-Line Memory Module . 30 / 72 pin . 32 / 64 bits .
* DIMM : Dual In-Line Memory Module . 100 / 168 / 184 / 240 pin . ?(32) / 64 / 72 / ? bits . SDRAM (168pin) . DDR (184pin) . DDR2 (240pin) .
* SO-DIMM : Small Outline DIMM . 72 / 144 / 200 pin . 32 / 64 / 72(?) bits . SDRAM (144pin) . DDR (200pin) .
* SO-RIMM : Small Outline RIMM . 160 pin .
* FB-DIMM : Fully Buffered DIMM . Uses DDR2 .
* FB-DIMM2 : Will help DDR3 .
* MicroDIMM : DDR (172 pin) . DDR2 (214pin Mezzanine Connector) . Measure 65% of SO-DIMM .
* MiniDIMM : DDR2 (244pin)

SDRAM :
* PC 66 : SDRAM . (Clock/FSB & Data) 66 MHz x 8 Bytes = 0.53 GBps .
* PC 100 : SDRAM . 100 MHz x 8 Bytes = 0.8 GBps .
* PC 133 : SDRAM . 133 MHz x 8 Bytes = 1.06 GBps .
* PC 150 : SDRAM . 150 MHz x 8 Bytes = 1.2 GBps .
* PC 166 : SDRAM . 166 MHz x 8 Bytes = 1.33 GBps .
* PC 200 : SDRAM . 200 MHz x 8 Bytes = 1.6 GBps .

Rambus RDRAM :
* DRDRAM : Direct RDRAM . 16 / 18 bits . 600 / 800 MHz . 1.2 / 1.6 GBps .
* Base, Concurrent RDRAM : 8 / 9 bits. 700 MHz. 0.7 GBps .
* RIMM : Rambus Incorporation/In-Line Memory Module . 184 pin (16 bit) . 232 pin (32 bit) .
* PC 800 Single Channel RDRAM : 16 bits version . 2 Bytes x 800 MHz (Data Rate) (400 MHz Clock x 2 (Double Pumped)) = 1.6 GB/s .
* PC 1066 Double/2/Dual Channel RDRAM : 32 bits Version x 2 Channel (Total is 64 bits) = 4 Bytes x 1066 MHz (Data Rate) (533 MHz Clock x 2 (Double Pumped)) x 2 Channel = 8.5 GB/s . 64 bits Version 2 Ch BW is 17.05 GB/s .
* PC 1066 Quad/4 Channel RDRAM : 32 bits Version x 4 Channel (128 bits) = 4 Bytes x 1066 MHz (Data Rate) (533 MHz Clock x 2 (Double Pumped)) x 4 Channel = 17.05 GB/s . 64 bits Version 4 Ch BW is 34.1 GB/s .
* PC 1200 : (Ext/FSB) Clock 600 MHz . Data Clock 1200 Mbps . 2 Ch BW is 4.8 GB/s .

SLDRAM / DDR2 . SyncLink DRAM . 16 bits . 800 MHz . 1.6 GBps .
DDR2 SDRAM . 64 bits . 400 MHz . 3.2 GBps .

* XDR : Extreme Data Rate DRAM :

* FSB = Front Side Bus . The data path that runs between the CPU and main memory (RAM) and motherboard's chipset . Also known as HTT for AMD (Athlon64, etc) processors . For example, Intel system bus (CPU to bus interface) = 64 bits x 800 MHz FSB (effective data rate) / 8 (bit to byte conversion) = BW is 6.4 GB/s . AMD (Athlon64) CPU have no traditional FSB, instead uses HTT (200 ~1600 MHz) .
* HT = HyperTransport Technology or "HyperTransport" (Also known as HTT : HyperTransport Technology) . Bus . HT formerly known as LDT, is a bidirectional serial/parallel high-bandwidth, low-latency computer bus / tunnel . The HyperTransport Technology Consortium is in charge of promoting and developing HyperTransport technology . HTT x CPU multiplier = CPU core speed . Functionaly, AMD's HTT is not (at all) same as HTT used in Intel processors . For example, AMD socket 754 processor has a HTT speed of 800 MHz, which equals to (effective) Data Transfer Rate of (800 x 2 =) 1600 MT/s (because of DDR) . So FSB is 1600 MHz (but, to say it correctly, HTT is 800 MHz or 1600 MT/s) . Memory Clock Index value or reference clock is 200 MHz (for most MoBo, for that type of processor), so with HTT Multipler at x4, HTT is (200 x 4 =) 800 MHz . Also see HT, FSB . HyperTransport supports an auto-negotiated bus widths, based on two 2-bit lines to 32-bit lines . The full-sized, full-speed 32-bit bus in each direction has a transfer rate of 22.4 GB/s . HyperTransport is packet-based, the first word in a packet is always a command word . If a packet contains an address, the last 8 bits of the command word are chained with the next 32-bit word to make a 40-bit address . The remaining 32-bit words in a packet are the data payload . HyperTransport revision 1.05 contains an option allowing an additional 32-bit control packet to be prepended when 64-bit addressing is required . It is Full Duplex (it can send and receive data at the same time) . For example, AMD Athlon64 CPU (939 pin) to HT interconnect bus (HTT) = 32 bit bus (16 bit up + 16 bit down bi-directional full duplex) x 2000 MHz (effective data rate) / 8 (bit to byte conversion) = 8.0 GB/s . Older, Socket 754 and 940 (pin) chips run at 1600 MHz (effective) bus and equals to 6.4 GB/s bandwidth .
* HTT = Hyper-Threading (HT) Technology (HTT) . Also see HT, FSB . Intel's SMT was introduced as HTT . Intel's HTT delivered two (logical) processors that could execute different tasks simultaneously using shared hardware resources . Advanced form of Super-threading . Functionaly, Intel's HTT is not (at all) same as HTT used in AMD processors . SMP support in the operating system can take advantage of HTT . HTT uses TLP, MLP .
* CPU = Central Processing Unit . Processor . Active part of a computer, where mathemetical, logical, data processing, etc operations are performed .
* IC = Integrated Circuit . an IC is a very small electronic device made out of different components, most of these components are made out of different type of semiconductor materials .
* ECC = Error Correction Code . x72 . ECC modules usually have one extra memory chip . For 64 bit (x64), extra 8 bit are added for ECC, so total bit becomes (64 + 8 =) 72 bit .
* SPD = Serial Presence Detect . Most SDR/DDR Module have SPD chip . It consists of serial (1-bit I/O) EEPROM, and contains memory module specification information such as the DRAM type, capacity, access speed, etc .
* SMT = Simultaneous MultiThreading . Also see HTT .
* TLP = Thread Level Parallelism .
* MLP = Memory Level Parallelism .
* LDT = Lightning Data Transport . Same as HTT (used in AMD) . Also used for HTT multiplier, or, LDT multiplier . Also see HT, HTT, FSB .
* SMP = Symmetric MultiProcessing .
* MoBo = Motherboard . Main board to attach processor, memory, hard-drive, etc . CPU board .
* Multi = Multiplier . CPU Multiplier . HTT, or, FSB Multiplier . For example, if a CPU spec has 9x (CPU) multi, then, with reference (DRAM) memory clock of 200 MHz, CPU frequency will be (200 x 9 =) 1.8 GHz . If (HT, or,) HTT multi (/LDT) is set to x5, and ref. memory clock is (set at) 200 MHz, then HTT bus speed is (200 x 5 =) 1000 Mhz .
* CPU Multi = CPU/FSB Frequency Ratio . Also see Multi .
* LDT Multi = LDT/FSB Frequency Ratio . Also see Multi .
* HTT Multi = HTT/FSB Frequency Ratio . Also see Multi .
* FSB Frequency Ratio = DRAM : FSB frequency ratio . If FSB = 200 MHz, then 100 Mhz memory have 1/02 ratio, 120 Mhz (3/05), 133 Mhz (2/03), 140 Mhz (7/10), 150 Mhz (3/04), 166 Mhz (5/06), 180 Mhz (9/10), 200 Mhz (1/01) . Also see (below) DRAM frequency chart .
* AGP = 66 MHz .
* PCI = 33 MHz .
* PCI Express = 100 MHz .
* Channel = Bus . Path . Memory Controller bus . For example, AMD Socket 939 processors have dual (2 x 64 bit) channel memory controller (DC-MCT), whereas Socket 754 have single (64 bit) channel MCT . DC-MCT requires at least two memory (DIMM) module . DC-MCT not only have higher Bandwidth but also benefitting from addressing each module from both MCT .
Whereas single channel MCT, addresses all modules . Quad (or Octal) channel MCT have more higher throughput bandwidth and can serve multiple data at same clock .
* Memory Frequency = FSB x (CPU multi) / C . Where, C (Ceiling function) = (CPU multi) x (FSB : DRAM ratio), or, (CPU multi) / (DRAM:FSB ratio) . When C is positive fractional number, round up it to the nearest (higher positive) whole number, for correct C and right before you apply C in Mem.Freq. formula . When C is negative fractional number, round down it to the nearest (lower negative) whole number . For example, if FSB = 233 MHz, CPU multi = 10 and DRAM:FSB ratio = 4:5, then, 1st re-arrange DRAM:FSB as FSB : DRAM ratio . So, it is 5:4 . (5 / 4 =) 1.25 . 2nd, we will find C . C = 10 x 5 / 4 = 12.5 . Now after applying the rounding rules, we get, 13 . Now, Mem.Freq. = 233 x 10 / 13 = 179.23 MHz .
* CPC = Command Per Clock . Command Rate .

More Info :
The Definitive DFI A64 Overclocking Guide at Dfi-Street.com : http://www.dfi-street.com/forum/showthread.php?t=20823

[tareek]

Chapter 03 :

DDR SDRAM :

• PC 1600 : DDR 200 : 64 bits, 8 Bytes x 200 MHz (Data (Transition) Rate) (100MHz Clock (FSB) x 2 (Double Pumped)) = 1.6 GB/s . (128 bits DCT BW is 3.2 GB/s) .
• PC 2100 : DDR 266 : 64 bits, 8 Bytes x 266 MHz (133MHz Clock (FSB) x 2 (Double Pumped)) = 2.1 GB/s . (128 bits DCT BW is 4.2 GB/s) .
• PC 2400 : DDR 300 : 64 bits, 8 Bytes x 300 MHz (150MHz Clock (FSB) x 2 (Double Pumped)) = 2.4 GB/s . (128 bits DCT BW is 4.8 GB/s) .
• PC 2700 : DDR 333 : 64 bits, 8 Bytes x 333 MHz (166MHz Clock (FSB) x 2 (Double Pumped)) = 2.7 GB/s . (128 bits DCT BW is 5.33 GB/s) .
• PC 3200 : DDR 400 : 64 bits, 8 Bytes x 400 MHz (200MHz Clock (FSB) x 2 (Double Pumped)) = 3.2 GB/s . (128 bits DCT BW is 6.4 GB/s) .
• PC 3700 : DDR 466 : 64 bits, 8 Bytes x 466 MHz (233MHz Clock (FSB) x 2 (Double Pumped)) = 3.7 GB/s . (128 bits DCT BW is 7.4 GB/s) .
• PC 4200 : DDR 533 : 64 bits, 8 Bytes x 533 MHz (266MHz Clock (FSB) x 2 (Double Pumped)) = 4.2 GB/s . (128 bits DCT BW is 8.5 GB/s) .
• PC 4800 : DDR 600 : 64 bits, 8 Bytes x 600 MHz (300MHz Clock (FSB) x 2 (Double Pumped)) = 4.8 GB/s . (128 bits DCT BW is 9.6 GB/s) .
• PC 5300 : DDR 667 : 64 bits, 8 Bytes x 667 MHz (333MHz Clock (FSB) x 2 (Double Pumped)) = 5.3 GB/s . (128 bits DCT BW is 10.6 GB/s) .
• PC 5800 : DDR 733 : 64 bits, 8 Bytes x 733 MHz (366MHz Clock (FSB) x 2 (Double Pumped)) = 5.8 GB/s . (128 bits DCT BW is 11.7 GB/s) .
• PC 6400 : DDR 800 : 64 bits, 8 Bytes x 800 MHz (400MHz Clock (FSB) x 2 (Double Pumped)) = 6.4 GB/s . (128 bits DCT BW is 12.8 GB/s) .
• PC 6900 : DDR 866 : 64 bits, 8 Bytes x 866 MHz (433MHz Clock (FSB) x 2 (Double Pumped)) = 6.9 GB/s . (128 bits DCT BW is 13.8 GB/s) .
• PC 7500 : DDR 933 : 64 bits, 8 Bytes x 933 MHz (466MHz Clock (FSB) x 2 (Double Pumped)) = 7.4 GB/s . (128 bits DCT BW is 14.9 GB/s) .
• PC 8000 : DDR 1000 : 64 bits, 8 Bytes x 1000 MHz (500MHz Clock (FSB) x 2 (Double Pumped)) = 8.0 GB/s . (128 bits DCT BW is 16.0 GB/s) .
• PC 8500 : DDR 1066 : 64 bits, 8 Bytes x 1066 MHz (533MHz Clock (FSB) x 2 (Double Pumped)) = 8.5 GB/s . (128 bits DCT BW is 17.07 GB/s) .

"PC-xxxx" expresses theoretical bandwidth (often, the value is rounded up or down) . "DDR-nnn", or, "DDR-nnnn" expresses effective clockspeed . Bandwidth (xxxx) is calculated from the "effective clockspeed" (nnn, or, nnnn) and multiplying it with eight(8) . DDR is 64-bit memory, there are 8 bits in a byte, and 64 bits divided by 8 is 8 .
Double Pumped = DP = Dual Edge Clock Rate Data Transfer .
The Registered DIMM requires a (onboard) buffer, are more expensive than unbuffered DIMMs . But Unbuffered DIMMs are 1 clock cycle faster than Registered DIMM .

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Chapter 04 :

DDR2 SDRAM :

• PC2-3200 : DDR2-400 : 64 bits. 8 Bytes x 400 MHz (Data Transition Rate Clock) ((100 MHz (Core) Clock x 2 (I/O Clock)) = 200MHz (FSB) x 2 (DP)) x 1 Ch = 3.2 GB/s . Dual(2) Ch BW is 6.4 GB/s . 128 bit DCT 1 Ch BW 6.4 GB/s, 2 Ch BW 12.8 GB/s .
• PC2-4300 : DDR2-533 : 64 bits. 8 Bytes x 533 MHz ((133 MHz Clock x 2 (I/O Clock)) = 266MHz (FSB) x 2 (DP)) x 1 Ch = 4.2 GB/s . 2 Ch BW is 8.5 GB/s . 128 bit DCT 1 Ch BW 8.5 GB/s, 2 Ch BW 17.0 GB/s .
• PC2-5400 : DDR2-667 : 64 bits. 8 Bytes x 667 MHz ((166 MHz Clock x 2 (I/O Clock)) = 333MHz (FSB) x 2 (DP)) x 1 Ch = 5.3 GB/s . 2 Ch BW is 10.6 GB/s . 128 bit DCT 1 Ch BW 10.6 GB/s, 2 Ch BW 21.3 GB/s .
• PC2-6400 : DDR2-800 : 64 bits. 8 Bytes x 800 MHz ((200 MHz Clock x 2 (I/O Clock)) = 400MHz (FSB) x 2 (DP)) x 1 Ch = 6.4 GB/s . 2 Ch BW is 12.8 GB/s . 128 bit DCT 1 Ch BW 12.8 GB/s, 2 Ch BW 25.6 GB/s .
• PC2-8500 : DDR2-1066 : 64 bits. 8 Bytes x 1066 MHz ((266 MHz Clock x 2 (I/O Clock)) = 533MHz (FSB) x 2 (DP)) x 1 Ch = 8.5 GB/s . 2 Ch BW is 17.0 GB/s . 128 bit DCT 1 Ch BW 17.0 GB/s, 2 Ch BW 34.1 GB/s .
• PC2-9600 : DDR2-1200 : 64 bits. 8 Bytes x 1200 MHz ((300 MHz Clock x 2 (I/O Clock)) = 600MHz (FSB) x 2 (DP)) x 1 Ch = 9.6 GB/s . 2 Ch BW is 19.2 GB/s . 128 bit DCT 1 Ch BW 19.2 GB/s, 2 Ch BW 38.4 GB/s .
• PC2-10672 : DDR2-1334 : 64 bits. 8 Bytes x 1334 MHz ((333 MHz Clock x 2 (I/O Clock)) = 667MHz (FSB) x 2 (DP)) x 1 Ch = 10.6 GB/s . 2 Ch BW is 21.3 GB/s . 128 bit DCT 1 Ch BW 21.3 GB/s, 2 Ch BW 42.6 GB/s .
• PC2-11728 : DDR2-1466 : 64 bits. 8 Bytes x 1466 MHz ((366 MHz Clock x 2 (I/O Clock)) = 733MHz (FSB) x 2 (DP)) x 1 Ch = 11.7 GB/s . 2 Ch BW is 23.4 GB/s . 128 bit DCT 1 Ch BW 23.4 GB/s, 2 Ch BW 46.9 GB/s .
• PC2-12800 : DDR2-1600 : 64 bits. 8 Bytes x 1600 MHz ((400 MHz Clock x 2 (I/O Clock)) = 800MHz (FSB) x 2 (DP)) x 1 Ch = 12.8 GB/s . 2 Ch BW is 25.6 GB/s . 128 bit DCT 1 Ch BW 25.6 GB/s, 2 Ch BW 51.2 GB/s .

"PC2-xxxx", or, "PC2-xxxxx" expresses theoretical bandwidth (often, the value is rounded up or down) . "DDR2-nnn", or, "DDR2-nnnn" expresses effective clockspeed . Bandwidth (xxxx, or, xxxxx) is calculated from the "effective clockspeed" (nnn, or, nnnn) and multiplying it with eight(8) . DDR2 is 64-bit memory, there are 8 bits in a byte, and 64 bits divided by 8 is 8 .

[tareek]

Chapter 05 :

FB-DIMM SDRAM :
240 pin . 1.5v . Utilizes DDR2 . 133.5mm long . The notch key is 8mm right of center (or 74.68mm from left side) . FB-DIMM modules are Fully-Buffered (on-board) . The high-speed Advanced Memory Buffer (AMB) chip is located on each FB-DIMM, it collects and distributes the data from or to the DRAMs on the DIMM, buffers the data internally on the chip and forwards or receives it to the next DIMM or memory controller . Unlike other normal DIMM modules which are connected in parallel (multi-drop-bus) to the memory controller (off a stub), FB-DIMM modules are connected in a point-to-point serial architecture . Max 8 DIMMs Per Ch .

• PC2-4200 : DDR2-533 . Clock Speed 266 MHz . Data Rate 533 MHz . Through-put (64 bit 1 Ch) 4.26 GB/s, 64 bit 2 Ch BW 8.53 GB/s, 64 bit 4 Ch BW 17.05 GB/s .
• PC2-5300 : DDR2-667 . Clock Speed 333 MHz . Data Rate 666 MHz . Through-put (64 bit 1 Ch) 5.33 GB/s, 64 bit 2 Ch BW 10.67 GB/s, 64 bit 4 Ch BW 21.34 GB/s .
• PC2-6400 : DDR2-800 . Clock Speed 400 MHz . Data Rate 800 MHz . Through-put (64 bit 1 Ch) 6.4 GB/s, 64 bit 2 Ch BW 12.8 GB/s, 64 bit 4 Ch BW 25.6 GB/s .
• PC2-7400 : DDR2-933 . Clock Speed 466 MHz . Data Rate 933 MHz . Through-put (64 bit 1 Ch) 7.46 GB/s, 64 bit 2 Ch BW 14.93 GB/s, 64 bit 4 Ch BW 29.85 GB/s .
• PC2-8500 : DDR2-1066 . Clock Speed 533 MHz . Data Rate 1066 MHz . Through-put (64 bit 1 Ch) 8.53 GB/s, 64 bit 2 Ch BW 17.05 GB/s, 64 bit 4 Ch BW 34.11 GB/s .
• PC2-9600 : DDR2-1200 . Clock Speed 600 MHz . Data Rate 1200 MHz . Through-put (64 bit 1 Ch) 9.6 GB/s, 64 bit 2 Ch BW 19.2 GB/s, 64 bit 4 Ch BW 38.4 GB/s .
• PC2-10600 : DDR2-1333 . Clock Speed 667 MHz . Data Rate 1333 MHz . Through-put (64 bit 1 Ch) 10.66 GB/s, 64 bit 2 Ch BW 21.33 GB/s, 64 bit 4 Ch BW 42.65 GB/s .
• PC2-11700 : DDR2-1466 . Clock Speed 733 MHz . Data Rate 1466 MHz . Through-put (64 bit 1 Ch) 11.73 GB/s, 64 bit 2 Ch BW 23.45 GB/s, 64 bit 4 Ch BW 46.91 GB/s .
• PC2-12800 : DDR2-1600 . Clock Speed 800 MHz . Data Rate 1600 MHz . Through-put (64 bit 1 Ch) 12.8 GB/s, 64 bit 2 Ch BW 25.6 GB/s, 64 bit 4 Ch BW 51.2 GB/s .

"PC2-xxxx", or, "PC2-xxxxx" expresses theoretical bandwidth (often, the value is rounded up or down) . "DDR2-nnn", or, "DDR2-nnnn" expresses effective clockspeed . Bandwidth (xxxx, or, xxxxx) is calculated from the "effective clockspeed" (nnn, or, nnnn) and multiplying it with eight(8) .

[tareek]

Chapter 06 :

DDR3 SDRAM :

• PC3-6400 : DDR3-800 : Data Rate Clock Transition 800 MHz . (100 MHz (Core) Clock x 8 (Octal Edge)) . (Data Clock 400 MHz (FSB) x 2 DP) . 64 bit 1 Ch BW is 6.40 GB/s, 2 Ch BW is 12.80 GB/s, 4 Ch BW is 25.60 GB/s . 128 bit 1 Ch BW is 12.80 GB/s, 2 Ch BW is 25.60 GB/s, 4 Ch BW is 51.20 GB/s .
• PC3-8500 : DDR3-1066 : Data Rate Clock Transition 1066 MHz . (133 MHz Clock x 8 (Octal Edge)) . (Data Clock 533 MHz (FSB) x 2 DP) . 64 bit 1 Ch BW is 8.53 GB/s, 2 Ch BW is 17.05 GB/s, 4 Ch BW is 34.11 GB/s . 128 bit 1 Ch BW is 17.05 GB/s, 2 Ch BW is 34.11 GB/s, 4 Ch BW is 68.22 GB/s .
• PC3-10667 : DDR3-1333 : Data Rate Clock Transition 1333 MHz (167 MHz Clock x 8 (Octal Edge)) . (Data Clock 667 MHz (FSB) x 2 DP) . 64 bit 1 Ch BW is 10.66 GB/s, 2 Ch BW is 21.32 GB/s, 4 Ch BW is 42.65 GB/s . 128 bit 1 Ch BW is 21.32 GB/s, 2 Ch BW is 42.65 GB/s, 4 Ch BW is 85.31 GB/s .
• PC3-12800 : DDR3-1600 : Data Rate Clock Transition 1600 MHz (200 MHz Clock x 8 (Octal Edge)) . (Data Clock 800 MHz (FSB) x 2 DP) . 64 bit 1 Ch BW is 12.80 GB/s, 2 Ch BW is 25.60 GB/s, 4 Ch BW is 51.20 GB/s . 128 bit 1 Ch BW is 25.60 GB/s, 2 Ch BW is 51.20 GB/s, 4 Ch BW is 102.40 GB/s .
• PC3-14900 : DDR3-1866 : Data Rate Clock Transition 1866 MHz (233 MHz Clock x 8 (Octal Edge)) . (Data Clock 933 MHz (FSB) x 2 DP) . 64 bit 1 Ch BW is 14.93 GB/s, 2 Ch BW is 29.85 GB/s, 4 Ch BW is 59.71 GB/s . 128 bit 1 Ch BW is 29.85 GB/s, 2 Ch BW is 59.71 GB/s, 4 Ch BW is 119.42 GB/s .

"PC3-xxxx", or, "PC3-xxxxx" expresses theoretical bandwidth . "DDR3-nnn", or, "DDR3-nnnn" expresses effective clockspeed . Often, these values are rounded up or down . Bandwidth (xxxx, or, xxxxx) is calculated from the "effective clockspeed" (nnn, or, nnnn) and multiplying it with eight(8) .

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Chapter 07 :

Typical Power Dissipation (Approximate) :
A DDR DIMM needs 5.4 watts, a DDR2 DIMM needs 4.4 watts and a DDR2 FB-DIMM needs 10.4 watts .

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Chapter 08 :

Architecture, Speed, Bandwidth and Thermal/Power Comparison :

    Core Speed     Prefetch          Peak BW
       (RPM)        (Gear)            (MPH)
DDR-200

                                    2.1   2.6
                     |1|                o  o   
   133  o o  167     | |      -> 1.6  o      o  3.2
      o     o        |-|            o  \       o
100  o <-+   o  200  |2|<-    1.1  o    \       o
      o     o        |-|           o     +      o
        o o          | |            o          o
                     |4|              o      o
                                         o o  


DDR-400
                                    2.1   2.6
                     |1|                o  o   
   133  o o  167     | |         1.6  o      o  3.2 <-
      o     o        |-|            o      /   o
100  o   +-> o  200  |2|<-    1.1  o      /     o
      o     o        |-|           o     +      o
        o o          | |            o          o
                     |4|              o      o
                                         o o
    Core Speed     Prefetch          Peak BW
       (RPM)        (Gear)            (MPH)

    Core Speed     Prefetch          Peak BW
       (RPM)        (Gear)            (MPH)
DDR2-400
                                    2.1   2.6
                     |1|                o o   
   133  o o  167     | |         1.6  o     o  3.2 <-
      o     o        | |            o      /  o
100  o <-+   o  200  |2|      1.1  o      /    o
      o     o        | |           o     +     o
        o o          |-|            o         o
                     |4|<-            o     o
                      -                 o o  


DDR3-800
                                    2.1   2.6
                     |2|                o o   
   133  o o  167     | |         1.6  o     o   3.2
      o     o        | |            o         o
100  o <-+   o  200  |4|      1.1  o           o  4.2
      o     o        | |           o     +     o
        o o          |-|            o   /     o  4.8
                     |8|<-           o /     o
                      -        -> 6.4  o   o   5.3 
                                        5.8 
    Core Speed     Prefetch          Peak BW
       (RPM)        (Gear)            (MPH)

Higher pre-fetch reduces core cycle time and reduces DRAM core power usage . Lower I/O & core voltage reduces overall power usage, thus reduces heat generation . 1KB page reduces activate power usage . Option to disable DLL, reduces powerdown power usage .

[tareek]

Chapter 09 :

Memory Timings Format :

CAS-tRCD-tRP-tRAS

Where each number is in clock-cycles .

For example,
if a good DDR-400 memory (at 200 MHz clock with a 5 ns cycle time) is rated 2-2-2-5,
then,
CAS = 10 ns, tRCD = 10 ns, tRP = 10 ns, tRAS = 25 ns .
total is 55 ns .

Timings for Read (tRCD-R) and Write (tRCD-W) is different in DDR3 . tRCD for read and write, is same for other SDRAM .

You may also find memory timings in below format
CAS-tRCD-tRP-tRAS-CMD

For example, Kingston HyperX PC4300 memory module has these specifications Vdimm=2.7 Volts and 3-4-4-8 timings . It means, it can run up to 4300/16=268.75 MHz, without problems for any system if Vdimm=2.7Volts and timings 3-4-4-8 . Where, the divider, 16, is recommended by the Manufacturer to find MSF .

* CAS = Column Address Strobe, or, Column Address Select . This is the last stage in actually finding the proper data, so it's the most important step of memory timing . It primarily finds & controls the memory columns, within the memory matrix . when RAS finds the row (one half of the (hex) address) for the required data, tRCD is started, and when tRCD ends, CAS starts .
* RAS = Row Address Strobe .
* tRCD = RAS to CAS Delay . Row Address to Column Address Delay . RAS is activated when data is first requested (first stage), and, CAS is activated when RAS is complete (second stage) . There is an interval between RAS and CAS, as memory can't locate a block precisely in a single stage .
* tRP = RAS Precharge . Row Precharge Time . the amount of time, taken by memory to end the access in one row and begin another . this, follows, right after data is set to the pins and activates tRAS, then RAS, tRCD, and CAS .
* tRAS = Active to Precharge Delay . Row Active Time (or, Cycle Time in CPUz) . tRAS = tRCD + CAS + 2 . values lower than that will drop performance, and, higher values will introduce unnecessary wait . For example, if you're using a tRCD of 3, and a CAS of 2, then you should set tRAS to 7 . This is the first stage in finding the proper data . the amount of time taken, in between, receiving a request for data (electronically) on the pins of a memory module and then initiating RAS to start the actual retrieval of data . Data requested electronically is "precharge", and the memory actually going to initiate RAS is "activation" .
* CMD = Command rate . CMD rate is generally used, to describe the amount of time, starting from a chip select (CS), until a Row Activate Command can be given . The chip select defines the physical bank in which the row is located . system running a single, single-sided memory module, have only one bank , whereas a double-sided module have two banks . many mobo chipset (i.e; Intel) supports only four banks per memory channel, thus lacking variable CMD rate .
* CL = CAS Latency . tCL . ns .
* SPL = Serial Presence Detect . Small Chip on Memory Module . Contains internal information related to the RAM Module's size, speed, etc .
* BL = Burst Length .
* WE = Write Enable .
* ns = nano second . Time . Duration . One Billionth of a second . 1 / 1 x 10^9 . (1 ms is 1 / 1 x 10^3) .
* Clock Cycle Time = Time duration of each cycle(/Hertz), in the memory bus . Most times, have same speed/frequency as FSB . To obtain cycle time duration from the bus frequency, increase the FSB frequency to the next unit of 1000 and divide it with the FSB frequency . For example, for a 200 MHz bus, divide 1 billion with 200 million (1,000,000,000 / 200,000,000) which equals to 5 nanosecond (ns) cycle time .
* T = 1 / F . T = Time . F = Frequency . Hertz . Cycle .
* tCLK = System Clock Speed . Clock Frequency . MHz .
* tCK = Memory Bus Clock Speed . Clock Frequency . MHz .
* GUF = Guaranteed Usable Frequency . MUF = Maximum Usable Frequency . a 7ns module, can be operated at (MUF) max 143 MHz, but, it can be (very safely) operated at (GUF) 133 MHz .
* tRFC = Row Refresh Cycle Time . Min. Auto-Refresh to Active/Auto-Refresh Command Period .
* tREF = refresh cycle . (xxK/xxms) . The refresh cycle rules are expressed as, i.e; 8,192/64ms (or 8K/64ms) . Means that, 8,192 refresh cycles must be performed within 64ms to hold the data in the memory cells . Distributed Refresh . Burst Refresh .
* tAC = Access Time . Measured in ns . Amount of time requires from the start of the memory access until when the valid data is available for use is tAC .
* tCAC = Column Access Time . ns .
* Vdimm, VDDR = RAM voltage . Vcore = CPU voltage . Vcc_HT = Hyper Transport bus (A64 systems) voltage . Vdd = Chipset voltage . VDDQ = Voltage of Memory Chip's Output Buffer . Vagp = AGP card voltage .
* RAM/FSB = Frequency Ratio . 1:2 means, if RAM is 100MHz, then FSB is at 200MHz .
* MSF = Maximum Stable Frequency . Hz .
* Hyper Transport speed = HT ratio (or LDT in some mainboards) X HTT . Hz . Also known as FSB speed, also see (above) FSB, HTT, HT, LDT . HTT x CPU multiplier = CPU core speed .


More Info :
RAM section of OverClocking Guide at OCTech.gr : http://octech.gr/forum/viewtopic.php?p=3237#3237

[tareek]

Chapter 10 :

Cycle  | f = Max. | Bandwidth SDR    | Bandwidth DDR 
Time T | Frequency| GB/s             | GB/s
-------|----------|--------------------------------------------
10 ns  | 100 MHz  | 0.8 GB/s (PC100) | 1.6 GB/s (DDR200/PC1600) 
7.5 ns | 133 MHz  | 1.06 GB/s (PC133)| 2.1 GB/s (DDR266/PC2100) 
6 ns   | 166 MHz  | 1.33 GB/s (PC166)| 2.7 GB/s (DDR333/PC2700) 
5 ns   | 200 MHz  | 1.6 GB/s (PC200) | 3.2 GB/s (DDR400/PC3200) 
4.29 ns| 233 MHz  | 1.86 GB/s (PC233)| 3.73 GB/s (DDR466/PC3700) 
3.76 ns| 266 MHz  | 2.13 GB/s (PC266)| 4.25 GB/s (DDR533/PC4200) 
3.33 ns| 300 MHz  | 2.4 GB/s (PC300) | 4.8 GB/s (DDR600/PC4800) 
3 ns   | 333 MHz  | 2.66 GB/s (PC333)| 5.33 GB/s (DDR667/PC5300) 
2.73 ns| 366 MHz  | 2.93 GB/s (PC366)| 5.85 GB/s (DDR733/PC5800) 
2.5 ns | 400 MHz  | 3.2 GB/s (PC400) | 6.4 GB/s (DDR800/PC6400) 
2.3 ns | 433 MHz  | 3.46 GB/s (PC433)| 6.92 GB/s (DDR866/PC6900) 
2.14 ns| 466 MHz  | 3.73 GB/s (PC466)| 7.45 GB/s (DDR933/PC7400) 
2 ns   | 500 MHz  | 4 GB/s (PC500)   | 8 GB/s (DDR1000/PC8000) 
1.87 ns| 533 MHz  | 4.26 GB/s (PC533)| 8.53 GB/s (DDR1066/PC8500) 
1.76 ns| 566 MHz  | 4.53 GB/s (PC566)| 9.05 GB/s (DDR1133/PC9000)

* BW = Bandwidth = Memory bus width / 8 bits x data rate .

[tareek]

Chapter 11 :

Identification :

Manufacturers Prefix Classification :

Manufacturer     | Prefixes  || Manufacturer | Prefixes 
-----------------|-----------||--------------|---------
Fujitsu          | MB, #     || Hitachi      | PDC, HM 
Hyundai/Hynix    | HY        || IBM          | IBM 
LG Semicon       | GM        || Micron Tech  | MT, USTEK, USA 
Mitsubishi       | M5M, M    || Mosel Vitelic| V 
IDT              | IDT       || NEC          | µPd, #, MC, MT
Samsung/SEC      | KM, K     || Motorola     | MCM 
Texas Instruments| TMS, TI   || Toshiba      | TC 
Corsair          | CM        || NPN          | NN 
Infineon         | HYB       || Siemens      | HYB 
Sharp            | LH        || Kingston     | KTM 
Alliance         | AS        || Panasonic    | MN 
Silicon Magic    | SM        || Seitec       | PM, DDR
ATE              | DDR, BF   || JetRAM       | J
BQ               | DDR       || Ram Bo       | RB
Nanya            | NT, N     || Galvantec    | GVT, MT 
Dimmax           | DM, PW    || Winbond      | W 
Life Time        | S         || Oki          | MSM, M, MSC, M5 
PNY              |           || Elpida       | E, DD, Elpida  
M-Tec            | TTD       || Mushkin      | W, TCCD
Crucial          | MT        || ProMos       |
Transcend        |           || GeIL         |
Apacer           | W, TCCD   || RamTron      |
Simpletech       |           || TwinMos      | TMD
Kingmax          | KDL       || Elixir       | N
PQI              | PQ        || Atl          | #
Eudar            | TMTCD, ES || Pluss        | IBG
A-Data           | ADD       || V-Data       | VDD
KTI              | TDL       || VT           | VT
VM               | VT        || ARC          | ARC
Semicon          | TM        || TG           | TG
AP               | DDR       || Winchip      | WT
Mr. STONE        | ITC       || Lei          | LED
Gold             | #         || PSC          | PSC, A
Buffalo          |           || Centon       | 
G.Skill          | TCCD      || Centon       |

PNY uses Siemens chips . Crucial Technology uses Micron Technology chips .

PCB = Printed Circuit Board . A PCB is a small (chassis) plate/board on which chips and other electronic components such as resistors, capacitors, inductors, transistors, semiconductor diodes, etc are placed/attached, and it also contains single or multiple layer(s) of wire connections in between those components .

Chips packaging :
Chips are available in a variety of IC(Integrated Circuit) package types and with different numbers of pins . Basic IC package types for memory chips include ball grid array (BGA), quad flat package (QFP), single in-line package (SIP), and dual in-line package (DIP) . Many packaging variants are available . For example, BGA variants include plastic-ball grid array (PBGA) and tape-ball grid array (TBGA) . QFP variants include low-profile quad flat package (LQFP) and thin quad flat package (TQFP) . DIPs are available in either ceramic (CDIP) or plastic (PDIP) . Other IC package types include small outline package (SOP), thin small outline package (TSOP), and shrink small outline package (SSOP) .
DDR2 BGA Chips :
Samsung 256Mbit 60 Ball Size : 11x13mm . Micron 256Mbit 60 Ball Size : 8x12mm . Elpida 256Mbit 84 Ball Size : 11x13mm . Infineon 256Mbit 60 Ball Size : 10x10.5mm . Hynix 256Mbit 60 Ball Size : 12x14mm .
60 pin FBGA is for x4 & x8, and 84 pin FBGA is for x16 components .

Form Factor :
* SDR SDRAM DIMM : 168 pin . 5.25" in (133.35 mm) (13.65 cm x 2.54 cm) long . Average width 1" in (2.54 cm) . Two notch . The center notch key is 2.625" from the left side . the other notch key is 0.925" from the left side .
* DDR SDRAM DIMM : 184 pin . 5.25" in long . One notch .
* DDR2 SDRAM DIMM : 240 pin . 5.25" in long . One notch .
* DDR MicroDIMM : 172 pin 2.5V .
* DDR2 MicroDIMM : 214 pin 1.8V .
* RIMM : 184 pin (16 bit) . 232 pin (32 bit) .
* SDRAM MicroDIMM : 144 pin . 1.545" x 1" (3.92 cm x 2.54 cm) .
* DDR SODIMM : 200 pin . 2.625" x 1" (6.67 cm x 2.54 cm) .
* DDR2 SODIMM : 200 pin . 2.625" x 1" (6.67 cm x 2.54 cm) .
* SDRAM SODIMM : 144 pin . 64 bit . 2.625" x 1" (6.67 cm x 2.54 cm) .
* SODIMM : 72 pin . 32 bit . 2.35" x 1" (5.99 cm x 2.54 cm) .
* DDR2 Mini Registered DIMM : 244 pin 1.8V .
* SIMM : 72 pin . 4.25" x 1" (10.8 cm x 2.54 cm) .

Unbuffered RAM :
ECC or non-ECC both version available . X64 (64 bit, non-ECC), X72 (72 bit, ECC) . ECC logic can correct/recover 1-bit data errors .

Registered RAM :
Alaways includes ECC . ECC modules have a 72-bit width (64 bits of data + 8 bits of ECC) . X72 . Performs data transfer via registers . A memory module containing Register chip(s) is/are used to relay and synchronize address and control signals issued by the motherboard's memory controller, and a Phase Locked Loop(PLL) chip is used to relay the motherboard's clock signal to all DRAM chips . The majority of server and workstation platforms require Registered DIMMs for very large memory capacity and reliability . Registered DIMMs for servers are available with x4 ("By 4")or x8 DRAM chips . x8-based server modules are the most cost-effective but only x4-based server modules can support server features, such as, multiple-bit error correction, Chip kill, memory scrubbing, and Intel Single Device Data Correction (SDDC) . Usually contains one extra memory chip than a similar non-ECC counterpart memory .

DRAM Organization :
x4 . x8 . x16 . x32 .

Performance Modules : When, (typically) any module is rated to perform above the market standard, is called Performance Modules . For Example : DDR800+, or, PC-6400 CL2 modules .

OEM (original equipment manufacturer) modules : is a confusing and misleading term . When a company uses original memory chips, to manufacture their own modules, and typically brands it(chip/module) with their own name, is OEM modules . This term, is not normally used, to describe a major or high quality modules . OEM modules are usually just built by using lower quality parts .

Third party modules : When a module manufactured by one company, uses chips built by another company, is 3rd party modules . For example, a module built by Kingston, when uses Samsung chips, is a third party module .

Major Original Brand modules : The standards of testing and manufacturing are normally higher, for the major brands .
Class1 (for average memory modules) : Samsung, Micron, Infineon, Hynix .
Class2 (for average memory modules) : Elpida, Mosel, Toshiba, Nanya .
All modules (from these Manuf.) cannot be judged in this way . Some Memory modules from a Class 2 Manuf can easily exceed a module built by a Class 1 Manuf.

Second Tier Original modules : Original modules were built by major manufacturers, but the testing standards were lowered, to sell into a more competitive market . Popular Examples : Spektec (Micron), Elixir (Nanya), Aeneon (Infineon) .

Downgrade modules : When memory modules are built by using downgraded chips, are often called half-bit modules . Some chips fall short of their intended standard and have to be passed down to a new standard . For example, a chip intended/made as 32M chips, but it failed to pass, but it passed successfully to be used as 16M chips .

Counterfeit Modules : The typical counterfeit case involves, using blank or UTT chips, being marked and illegally passed off as major brand chips . They are sold at a higher price, than their actual price . As the durability, quality, benchmark, testing standards, etc are not as good as a major brand modules, they fail and/or degrade quickly . Reputation of major brand companies suffers because of these modules .

UTT (UnTesTed) chips module : these chips are not as thoroughly tested, as major chips are tested . Often, UTT chips are remarked and distributed/sold as new specification, and also known as ETT (Effectively TesTed) chips/modules .


Test :
Memory chips are tested at the wafer probe level and also at the final package level . The tester used is usually rated as the ATE memory tester . This kind of tester usually cost several million dollars and is constructed as a fine time resolution programmable signal generator, with 100ps ~ 1ns step . Different techniques are available for testing DDR Memory modules, The two passes read tester, Real time controller tester, Native Environment Tester, Direct Socket Tester . DDR2 testers recently becoming available, CST tester . Few utility soft for memory test are, Memtest-86, MemTest, Sandra . Software for memory info : CPU-Z .

Heat Spreader : used for dissipating the heat generated by the chips into the air .

More Information :
Memory Database at TechPoerUp.com : http://www.techpowerup.com/memdb/
Identify DIMM Module's RAM Chip numbers : http://www.chipmunk.nl/DRAM/ChipManufacturers.htm
Delec Memory Guide : http://www.delec.com/guide/memory/
DRAM Technologies at PCGuide : http://www.pcguide.com/ref/ram/tech.htm
Ultimate Memory Guide at Kingston : http://www.kingston.com/tools/umg/
Crucial Information Library : http://www.crucial.com/library/
Different Articles on Memory at Tom's Hardware : http://www.tomshardware.com/motherbo...ory/index.html
Different Articles on Memory at OcTech.gr : http://octech.gr/forum/viewforum.php?f=24
Tech Details On Memory(RAM) at Doom9.org : http://forum.doom9.org/showthread.php?t=104139
FAQs at Elpida : http://www.elpida.com/en/contacts/faq.html
Memory Chips Photo by Tenjikan http://www.biwa.ne.jp/%7Eyok/TENJIKAN-DDR.htm
RAM Module Big List, Speed, Timing, Chip at DonanimHaber.com : http://forum.donanimhaber.com/m_938129/tm.htm
RAM Module, Timing, etc List at XtremeSystems.org : http://www.xtremesystems.org/forums/...ad.php?t=50010

[tareek]

Chapter 12 :

IBM POST Diagnostic Code Descriptions : Error Code 200 ~ 299 : Memory Error .

AMI BIOS Beep Codes : 2 to 5 Short Beeps : 1 Long & 3 Short Beeps : memory problems .

Phoenix BIOS Beep Codes : 1 pause 4 pause 2 beeps : 2 pause any# pause any# pause : some of memory is bad .

[tareek]

Chapter 13 :

For most dual-channel boards the memory modules must be identically sized, and have the same number and type of chips. Typically, the motherboard requires the modules to be inserted in pairs on either slot0 and slot1, or slot2 and slot3.

[tareek]

Chapter 14 :

=============================================================
         | DDR 266        | DDR 400        | DDR            |
FSB      |----------------|----------------|----------------|
Frequency| Mem:FSB=2:3    | Mem:FSB=1:1    | Mem:FSB=2:3    |
         | FSB:Mem=3:2    | FSB:Mem=1:1    | FSB:Mem=3:2    |
         |----------------|----------------|----------------|
         |BW 1Ch, 2Ch GB/s|BW 1Ch, 2Ch GB/s|BW 1Ch, 2Ch GB/s|
=========|================|================|================|
200 MHz  |133MHz (DDR 266)|200MHz (DDR 400)|                |
         |----------------|----------------|----------------|
         |2.12, 4.2 GB/s  |3.2, 6.4 GB/s   |                |
=========|================|================|================|
225 MHz  |150MHz (DDR 300)|225MHz (DDR 450)|                |
         |----------------|----------------|----------------|
         |2.4, 4.8 GB/s   |3.6, 7.2 GB/s   |                |
=========|================|================|================|
233 MHz  |155MHz (DDR 310)|233MHz (DDR 466)|                |
         |----------------|----------------|----------------|
         |2.48, 4.96 GB/s |3.72, 7.45 GB/s |                |
=========|================|================|================|
250 MHz  |166MHz (DDR 333)|250MHz (DDR 500)|                |
         |----------------|----------------|----------------|
         |2.66, 5.3 GB/s  |4, 8 GB/s       |                |
=========|================|================|================|
266 MHz  |177MHz (DDR 354)|266MHz (DDR 533)|                |
         |----------------|----------------|----------------|
         |2.83, 5.66 GB/s |4.26, 8.52 GB/s |                |
=========|================|================|================|
275 MHz  |183MHz (DDR 366)|275MHz (DDR 550)|                |
         |----------------|----------------|----------------|
         |2.92, 5.8 GB/s  |4.4, 8.8 GB/s   |                |
=========|================|================|================|
300 MHz  |200MHz (DDR 400)|300MHz (DDR 600)|                |
         |----------------|----------------|----------------|
         |3.2, 6.4 GB/s   |4.8, 9.6 GB/s   |                |
=========|================|================|================|
325 MHz  |216MHz (DDR 433)|325MHz (DDR 650)|                |
         |----------------|----------------|----------------|
         |3.46, 6.92 GB/s |5.2, 10.4 GB/s  |                |
=============================================================
         | DDR 266        | DDR 400        | DDR            |
FSB      |----------------|----------------|----------------|
Frequency| Mem:FSB=2:3    | Mem:FSB=1:1    | Mem:FSB=2:3    |
         | FSB:Mem=3:2    | FSB:Mem=1:1    | FSB:Mem=3:2    |
         |----------------|----------------|----------------|
         |BW 1Ch, 2Ch GB/s|BW 1Ch, 2Ch GB/s|BW 1Ch, 2Ch GB/s|
=========|================|================|================|
333 MHz  |222MHz (DDR 444)|333MHz (DDR 666)|                |
         |----------------|----------------|----------------|
         |3.55, 7.1 GB/s  |5.32, 10.65 GB/s|                |
=========|================|================|================|
350 MHz  |233MHz (DDR 466)|350MHz (DDR 700)|                |
         |----------------|----------------|----------------|
         |3.72, 7.45 GB/s |5.6, 11.2 GB/s  |                |
=========|================|================|================|
366 MHz  |244MHz (DDR 488)|366MHz (DDR 733)|                |
         |----------------|----------------|----------------|
         |3.9, 7.8 GB/s   |5.86, 11.72 GB/s|                |
=========|================|================|================|
375 MHz  |250MHz (DDR 500)|375MHz (DDR 750)|                |
         |----------------|----------------|----------------|
         |4, 8 GB/s       |6, 12 GB/s      |                |
=========|================|================|================|
400 MHz  |266MHz (DDR 533)|400MHz (DDR 800)|                |
         |----------------|----------------|----------------|
         |4.26, 8.52 GB/s |6.4, 12.8 GB/s  |                |
=========|================|================|================|

[tareek]

Chapter 15 :

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Chapter 16 :

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Chapter 17 :

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Chapter 18 :

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Chapter 19 :

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Chapter 20 :

... data ...

will be keep on adding more data, whenever possible .

enjoy .

thanks .