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Old 25th July 2023, 10:13   #1  |  Link
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Intel Introduces AVX10 for E-Cores to leverage AVX512

AVX512 support has been a bit of roller coaster ride for Intel, with Intel Xeon first supporting them, then being introduced to the i9 consumer CPUs, then phased out due to heat and throttling issues etc. Now with more and more mobile CPUs being made of Efficiency Cores (E Cores) and Performance Cores (P Cores), Intel was trying to find a way to leverage on the added capability of the performance cores while still being able to execute code, which is what led to AVX10. In other words, AVX10 will allow Intel CPUs that have both E Cores and P Cores to still support AVX-512, even though the actual 512 bit instructions will only really run on the latter (I mean on the P Cores). What's interesting about this is that the converged 256 bit AVX10 instructions code will be able to run on either the E Cores or the P Cores, thus allowing the CPU to still have support for AVX-512 capabilities. This is particularly important 'cause it was one of the fears (or rather obstacle) that rumors were pointing at when they mentioned that Intel could have disabled support for 512 bit vectors for those new CPUs as it did when it disabled them for both Alder Lake and Raptor Lake. Now, AVX10 can be thought as a "superset" of AVX512 and comes with all of its features and with both 256 bit and 512 bit vector register sizes.

To quote Intel:

AVX10 will include AVX512 vector instructions with an AVX512VL feature flag, a maximum vector register length of 256 bits as well as eight 32 bit mask registers and new versions of 256 bit instructions supporting embedded rounding

So, in a nutshell, AVX10 will allow those new CPUs to handle AVX512 but while the E cores will be limited to a vector length of max 256 bit the P cores will be able to handle the whole 512 bit vectors.

To quote Intel again:

existing applications will provide the same level of performance with AVX10 as they did with AVX-512, at least at the same vector lengths. AVX2 compiled applications, re-compiled to AVX10, should realize performance gains without the need for additional software tuning. AVX2 applications sensitive to vector register pressure will gain the most performance due to the 16 additional vector registers and new instructions. Highly-threaded vectorizable applications are likely to achieve higher aggregate throughput when running on E-core-based Intel Xeon processors or on Intel products with performance hybrid architecture.
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