x264 with MMX2 Support??

[chriszxl]

I guess T7200 ,Intel CoreDuo 2 ,Merom ,Dont have MMX2 support, but recent x264 codec always print this info:

using cpu capabilities: MMX2 SSE2Fast SSSE3 Cache64

Does the MMX2 opt. not only AMD cpu and the last intel cpu have ??

I'm really confused ...anyone help?

thanks..

[Dark Shikari]

Of course it has MMX2 support; all Intel CPUs Pentium 3 and later, along with all AMD CPUs Athlon and later, have MMX2.

[LoRd_MuldeR]

Can you explain what "MMX2" and "MMXEX" are? What is the difference to "normal" MMX?

I can't find any useful info on the web. If it all, I find some developer mailing lists that use (but don't explain) those terms.
Or I get something like "MMX2: MegaMan X2 (video game)" :p

Of course you can find a lot of info about MMX, but they never mention MMX2 or MMXEX ...

[imcold]

mmx2/mmxext/xmm is a subset of SSE that AMD included in their first K7 cpus, iirc (for example pshufw is a sse/mmxext instuction).

[LoRd_MuldeR]

mmx2/mmxext/xmm is a subset of SSE that AMD included in their first K7 cpus, iirc (for example pshufw is a sse/mmxext instuction).

I see. So Intel's CPUs support MMX2/MMXEX implicitly, because they are part of SSE...

[Sagittaire]

I see. So Intel's CPUs support MMX2/MMXEX implicitly, because they are part of SSE...

No it's simply historical evolution for optimised multimedia calculation. The first pentium introduce the MMX instructions ... later MMXExt, SSE, SSE2, SSE3, SSE4 ... etc. It's little like pixels shaders for GPU ...

[LoRd_MuldeR]

No it's simply historical evolution for optimised multimedia calculation. The first pentium introduce the MMX instructions ... later MMXExt, SSE, SSE2, SSE3, SSE4 ... etc. It's little like pixels shaders for GPU ...

Well, from what I understand now, there is no "MMXEXT" or "MMX2" on any Intel CPU. There is only MMX and SSE. Later SSE2 and so on.
There also is no need for MMXEXT or MMX2 on Intel CPU's, because they have SSE, which covers all the instructions from MMXEXT/MMX2..
AMD used MMXEXT/MMX2 until they implemented the whole SSE instruction set.

So there is a difference: MMX is not a subset of SSE, SSE is not a subset of SSE2, and so on. They all exist in parallel.
At the same time MMXEXT and MMX2 are subsets of SSE and thus become unnecessary as a separate extension, once you have SSE.

Correct me if that conclusion is wrong...

[akupenguin]

So there is a difference: MMX is not a subset of SSE, SSE is not a subset of SSE2, and so on. They all exist in parallel.
At the same time MMXEXT and MMX2 are subsets of SSE and thus become unnecessary as a separate extension, once you have SSE.

A computer supporting SSE4.1 is also guaranteed to support MMX1, MMX2, SSE1, SSE2, SSE3, and SSSE3. There is no point in distinguishing SSE4.1 from MMX1+MMX2+SSE1+SSE2+SSE3+SSSE3+SSE4.1. So the question of subset or not is purely semantics. The is no code you could write whose correctness depends on the answer, so I'm not going to argue it.

I will however say that any set of instructions supported by some cpu deserves a name. The name for the instructions supported by a certain generation of Athlon is MMX2. Given that such a name exists, it is simpler to talk about "a function that uses MMX2 instructions", rather than "a function that uses MMX2 and/or SSE1 instructions" which is what you would have to say if you pretended that MMX2 didn't exist on cpus with SSE1.

from what I understand now, there is no "MMXEXT" or "MMX2" on any Intel CPU.
Intel doesn't set the MMX2 bit in cpuid (the Intel ISA documentation (http://www.intel.com/design/processor/manuals/253666.pdf) doesn't even label that bit), but I as a software developer still have to infer MMX2's presence on Intel cpus.