@Midas - requests for azid v1.8.1

[DSPguru]

1. fast compiliation of azid.exe & azid.dll with icl7 (http://www.intel.com/software/products/compilers/downloads/cwin.htm).
2. native support for dolby surround2 matrix + "-s surround2" support in azid.exe & "ST_DSUR2" support in azid.dll
3. fix azid flaws. two samples can be found here (http://besweet.notrace.dk/azidflaw.zip).
4. avoid overflow messages when fullscale>1 (not solved yet, i'm afraid)

[Midas]

1) I would need some kind of license to do it. I've downloaded the link, but it seems useless without a license.

1b) Anyway, what about optimalizations for other processors? Like Athlon etc. etc. Are there specialized compilers for those?

2) I'm very sorry, but I've lost my files in a diskcrash. I know you sent me a description of DPL2, but can you please do it again? I should have no problem implementing DPL2, I just need to know the algorithm. And I dont have a DPL2 decoder either, so I cant verify the output.

3) Yes I'll certainly have a look at it...

4) When does this occur? (An example is very velcome)

5) I've got some requests about azid's diskhandling. It reads data from the disk in fairly small chunks, decodes it, and writes the litte chunk to disk again. People complain since this causes 50% CPU load (tops) and frantic disk activity on fast computers. Is there any point in me improving azids file handling? I mean, doesn't most people use the .dll in one form or another (besweet, etc. etc.)

[DSPguru]

1. i believe you can get a license for 30day of evaluation by email.
1b. icl can produce fast copmiles also for athlon. i can supply some switches if you like..
2. here are the downmix equations :
Lt=0.3225*fl+0.2280*c-0.2633*sl-0.1862*sr;
Rt=0.3225*fr+0.2280*c+0.1862*sl+0.2633*sr;
3. great.
4. i'll write something
5. i believe that 95% of azid users, are azid.dll users (HeadAC3He & BeSweet), so it's up to you..

[DSPguru]

//
// First of all the decoder must be initialized.
//
if(ac3_init()) {
fprintf(stderr,"%s: Cannot initialize ac3 decoder core\n",argv[0]);
fclose(infile);
return 1;
}


opts.speaker_gain[0]=100;
opts.fullscale=1000;

//
// Then some valid setting has to be registered.
//
if(ac3_regsettings(&opts)) {
fprintf(stderr,"%s: Cannot register settings\n",argv[0]);
ac3_free();
fclose(infile);
return 1;
}

-----
on run, you'll see the overflows.

ps,
dpl2 described above.

[Midas]

regards the downmix equations:

Isn't DPL2 more than just linear processing? I would bet that theres some signal processing involved, like phaseshift etc. for the rear channels to increase channel separation. Please look at:

http://www.dolby.com/tech/l.wh.0007.PLIIops.html

I dont know if the VCA stuff applies to the coder or not...

[DSPguru]

vca applies to the decoder.
in fact, most of the signal processing is done in the decoder.

as for the 90degrees phase shift, i believe it's done in the ac3 encoding stage. how do you currently apply dpl1 downmix ?
if you implement that phase shift, then keep it.
ps,the above equations were tested on azid's 6ch output and produced succesful results.

[MaTTeR]

Originally posted by DSPguru
1b. icl can produce fast copmiles also for athlon. i can supply some switches if you like.. This would be such a blessing:D

[Midas]

Here are the downmix equations :
Lt=0.3225*fl+0.2280*c-0.2633*sl-0.1862*sr;
Rt=0.3225*fr+0.2280*c+0.1862*sl+0.2633*sr;


Does anyone have a more theoretical/mathmatical basis of those numbers? Or are the number deducted by the trial/failure method?

I mean I use 32-bit float arithmetics in azid and to make DPL II work properly I need more accurate numbers. There is only roughly 13 bits of information is those numbers/constants above -- I need at least 20bits or 6 significant digits.

[DSPguru]

imho, the values should represent 10db, 11.5db, 13db, 14.5db.